Analog-digital converter

ABSTRACT

An analog-digital converter which comprises first and second signal input terminals selectively supplied with any of an input analog voltage and first and second reference voltages having the same polarity as said input analog voltage but different levels from each other; an integration circuit consisting of first and second integration resistors having substantially the same value of resistance and connected to the corresponding first and second input terminals, a D.C. amplifier provided with an inversion input terminal selectively connected to the first and second integration resistors and a noninversion input terminal impressed with a voltage whose level lies intermediate between those of the first and second reference voltages, and an integration capacitor connected between the output terminal of the D.C. amplifier and inversion input terminal; an analog comparator, one input terminal of which is connected to the output terminal of the D.C. amplifier and the other input terminal of which is impressed with a voltage having a reference level for comparison; and a control circuit including means for applying the first reference voltage to the first and second signal input terminals for a prescribed time T 1 , means for impressing the second reference voltage on the first and second signal input terminals and measuring a time T 2  required for an analog comparator to generate an output signal after coincidence is established between the levels of the second reference voltage and comparison reference voltage, means for determining a difference ΔT between the aforesaid times T 1 , T 2 , means for specifying a prescribed time T 3  according to said difference ΔT, and means for supplying the input analog voltage to the first signal input terminal only for the substantial first half T 3  /2 of said specified prescribed time T 3 , impressing the first or second reference voltage on the second signal input terminal, supplying the first signal input terminal with the reference voltage previously impressed during the first half T 3  /2 of said specified prescribed time T 3 , and conducting the input analog voltage to the second signal input terminal.

BACKGROUND OF THE INVENTION

This invention relates to an analog-digital converter (hereinafter abbreviated as "A-D converter") and more particularly to an A-D converter which can automatically carry out zero adjustment and full-scale adjustment with high precision and attain ratiometric conversion by causing an analog input voltage and reference voltage to have the same polarity, while adapting the dual slope system.

To date, a dual slope type A-D converter has been widely accepted. FIG. 1 shows the principle and circuit arrangement of the prior art A-D converter and FIG. 2 sets forth an operating waveform. Referring to FIG. 1, reference numeral V_(S) denotes an input voltage being measured; -V_(R) a reference voltage; V_(C) a comparison reference voltage; 1 a D.C. amplifier;and 2 an analog comparator. Where an input terminal 3 is impressed with the input voltage V_(S) for a prescribed time T₁ with switch means 4 set in the indicated condition, then an output voltage V_(O) from the D.C. amplifier 1 decreases from the reference level V_(C), as shown in FIG. 2. The angle of inclination presented by said decrease is defined by the time constant of an integration circuit, that is, a product arrived at by multiplying the resistance R of an input resistor and the capacitance C of an integration capacitor. Next, the operation of the switch means 4 is changed over to the input terminal 5 to supply an input voltage -V_(R) to the A-D converter. As the result, the output voltage V_(O) rises to intersect the reference level V_(C) in a time T₂. The angle of inclination shown by the increased output voltage V_(O) is also defined by the time constant C_(R) of the integration circuit. The following relationship is established between the fall and rise of the output voltage V_(O) :

    v.sub.s t.sub.1 + ( -v.sub.r)t.sub.2 + 0

thus (V_(S))/V_(R) = ( T₂ /T₁). Times T₁, T₂ are determined by counting clock pulses issued. In this case, the number of clock pulses counted during the time T₂ represents the A-D converted value of the input voltage V_(S).

The conventional dual slope type A-D converter is based on the above-mentioned principle. However, the dual slope system of FIG. 1 is accompanied with two noticeable drawbacks described below.

The first drawback is that where a time difference occurs in the A-D conversion due to the presence of the offset voltage ΔV of the D.C. amplifier 1, then the following ratio results between the levels of the input voltage V_(S) and referential voltage -V_(R).

    v.sub.s /v.sub.r = (1 - (Δv/v.sub.r)t.sub.2 /t.sub.1 - Δv/v.sub.r,

and consequently the ratio V_(S) /V_(R) fails to denote the ratio T₂ /T₁. To eliminate this drawback, various processes have been proposed, for example, the process of manually carrying out the zero adjustment and full-scale adjustment of the offset voltage of the D.C. amplifier 1 or effecting the zero and full-scale adjustments thereof by extracting the offset voltage to overlap it on the input voltage and reference voltage.

The second drawback is that the different polarities of the input voltage and reference voltage present difficulties in effecting ratiometric conversion. This ratiometric conversion can be only attained when the input voltage and reference voltage have the same polarity. With the prior art A-D converter, therefore, it was necessary for said ratiometric conversion to provide a voltage V_(R) having the same level as the reference voltage -V_(R) and the opposite polarity thereto. However, it was extremely difficult for forming of voltage of the positive and negative polarities to have exactly the same amplitude. Any difference in the amplitude directly led to errors in the operation of an A-D converter, making it impossible to obtain fully accurate values of ratiometric conversion.

Referring to the above-mentioned two noticeable drawbacks of the prior art A-D conversion, a number of automatic means have been proposed for the zero and full-scale adjustments of the offset of a D.C. amplifier, whereas no satisfactory method has been developed to realize accurate ratiometric conversion.

SUMMARY OF THE INVENTION

This invention has been accomplished in view of the above-mentioned circumstances and is intended to provide an A-D converter wherein the zero and full-scale adjustments of the offset of a D.C. amplifier can be automatically carried out exactly to the required degree of A-D conversion and input and reference voltages are made to have the same polarity, thereby attaining ratiometric conversion.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block circuit diagram of a prior art dual slope type A-D converter;

FIG. 2 is a graphic representation illustrating the operation of the A-D converter of FIG. 1;

FIG. 3 is a block circuit diagram of an A-D converter according to an embodiment of this invention;

FIGS. 4 and 5 graphically show the operation of the A-D converter of FIG. 3;

FIG. 6 is a block circuit diagram of a control circuit included in FIG. 3;

FIG. 7 indicates the operating condition of a counter included in FIG. 6;

FIG. 8 is a block circuit diagram of an A-D converter according to another embodiment of the invention;

FIG. 9 is a block circuit diagram of a control circuit used with the embodiment of FIG. 8;

FIGS. 10 and 11 are graphic representations illustrating the operation of an A-D converter using the control circuit of FIG. 12;

FIG. 12 is a block circuit diagram of a control circuit used with an A-D converter according to still another embodiment of the invention;

FIG. 13 presents the operating condition of the counter of FIG. 12;

FIG.14 is a block circuit diagram of an A-D converter according to still further embodiment of the invention; and

FIG. 15 graphically shows the operation of the circuit shown in FIG. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the embodiment of FIG. 3, input terminals 8, 9, 10 connected to an analog switch 14 are supplied with an input voltage V_(S), referential voltage V_(R) and grounding voltage O. An output signal from the analog switch 14 is conducted to an inversion input terminal of a D.C. amplifier 11 constituting an integrator I through two signal input terminals 13a, 13b and two integration resistors R₁, R₂ having substantially the same value of resistance. As in the embodiment of FIG. 8, the analog switch assembly 14 can deliver any of the three input voltages V_(S), V_(R), O to the selected one of the signal input terminals 13a, 13b. The noninversion input terminal of the D.C. amplifier 11 is impressed with a voltage having a level V_(R) /2 equal to half that of the referential voltage V_(R). The referential voltage input terminal of an analog comparator 12 is supplied with a comparison referential voltage V_(C). An output signal from the analog comparator 12 is carried to a control circuit 15, which, as later described, controls the operation of the changeover analog switch assembly 14 and also produces a digital output signal according to an analog input voltage.

The analog input voltage V_(S) and reference voltage V_(R) have the same polarity. The noninversion input terminal of the D.C. amplifier 11 is supplied with a voltage V_(R) /2. The D.C. amplifier 11 is connected to two integration resistors R₁, R₂ having the same value of resistance and integration capacitor C collectively to constitute an integrator. Referential numeral 12 denotes an analog comparator; 13a, 13b signal input terminals; and 14 a changeover switch assembly.

There will now be described the operation of an A-D converter embodying this invention, with the input voltage V_(S) and reference voltage V_(R) assumed to have a positive polarity alike. The signal input terminals 13a, 13b are supplied with any of V_(S), V_(R) and O (grounding voltage) in four ways, as shown in FIGS. 3 and 4, according to the operation of the changeover analog switch assembly 14. In this case, the control circuit 15 first sends forth a changeover control signal to the changeover switch assembly 14 so as to cause the signal input terminals 13a, 13b to be impressed alike with the referential voltage V_(R). When this condition of impression is continued for a prescribed time T₁, an output voltage V_(O) from the D.C. amplifier 11 decreases, as illustrated by the integration waveform of FIG. 4, during a period from point of point of time t_(O) to time t₁, that is, during said prescribed time T₁. Referring to FIG. 4, the output voltage V_(O) from the D.C. amplifier 11 is shown to begin to be impressed at a point represented by the level of the comparison reference voltage V_(C) for comparison by the analog comparator 12. In the practical process of impression, however, it is preferred that the supply of said output voltage V_(O) from the D.C. amplifier 11 be commenced from a point slightly higher level than that of the comparison reference voltage V_(C) so as to clearly define the point at which the starting point of said output voltage V_(O) intersects the level of the comparison reference voltage V_(C). The angle of an inclined line denoting the drop of the output voltage V_(O) during the prescribed time T₁ is determined by a value equal to half the time constant CR of the integrator I. When the reference voltage V_(R) has continued to be supplied for a prescribed time T₁, the movable contacts of the changeover switch assembly 14 have their positions changed, causing the input terminals 13a, 13b to be supplied with a grounding voltage 0. As the result, the output voltage V_(O) from the D.C. amplifier 11 continues to rise during a period from a point of time t₁ to a point of time period t₂, that is, during a time T₂ and reaches the level of the comparison reference voltage V_(C). Regarding the periods T₁, T₂, the following equation results ##EQU1## Therefore, T₁ and T₂ have the following relationship: ##EQU2##

Thus, the offset voltage at the noninversion input terminal of the D.C. amplifier 11 is expressed as ##EQU3## In this case, the relationship between T₂ and T₁ may be indicated as follows:

    T.sub.2 = T.sub.1 + ΔT

where:

ΔT = time difference resulting from ΔV.

Therefore, said time difference ΔT can be denoted as

    ΔT = T.sub.2 - T.sub.1

in the first stage of operation, two signal input terminals 13a, 13b are supplied with the reference voltage V_(R) for a prescribed time T₁. Later, both input terminals 13a, 13b are grounded, and measurement is made of a time period T₂ required for the level of the output voltage V_(O) to reach that of the comparison reference voltage V_(C). ΔT is determined from T₁ and T₂. This initial stage of operation allows for measurement of an amount of correction required for automatic adjustment. The level of said analog input signal is actually measured in the succeeding stage.

When the level of the output voltage V_(O) from the D.C. amplifier 11 reaches that of the comparison reference voltage V_(C) and the comparator 12 gives forth an output signal, then the input terminal 12a is supplied with an input voltage V_(S) and the input terminal 13b with a reference voltage V_(R) for a period from a point of time t₂ to a point of time t₃, that is, for the time period equal to half a period T₃ (assuming O ≦ V_(S) ≦ V_(R)). As a result, an output voltage V_(O) from the D.C. amplifier 11 decreases again. In this case, the time T₃ is defined in the same manner as the time T₁, in accordance with the following equation:

    T.sub.3 = T.sub.1 - 1/2ΔT

after the input terminal 13a is impressed with an input voltage V_(S) and the input terminal 13b with a reference voltage V_(R) for the first half of the time period T₃, the input terminal 13a is conversely supplied with a reference voltage V_(R) and the input terminal 13b with an input voltage V_(S) for the second half of the time period T₃. Later, both input terminals 13a, 13b are supplied with a grounding voltage 0. Measurement is again made of a time period T₄ extending from a point of time t₄ to a point of time t₅ which is required for the level of the output voltage V_(O) from the D.C. amplifier 11 to reach that of the comparison reference voltage V_(C).

The relationship between the time periods T₃ and T₄ is also expressed by the following equation: ##EQU4## Therefore, the ratio between the levels of the input voltage V_(S) and reference voltage V_(R) may be expressed as follows: ##EQU5## Since ΔT = T₂ - T₁, the above equation may be rewritten as follows: ##EQU6## Since T₃ = T₁ - 1/2ΔT, the above equation may be further changed as follows: ##EQU7## Thus the ratio between the levels of V_(S) and V_(R) may be approximately determined by the following equation: ##EQU8## where: T₁ = a known period in which a prescribed number of clock pulses are issued

T₄ = a time determined by measurement

ΔT = a value determined by calculating ΔT = T₂ - T₁

a = a suffix denoting approximation

Errors resulting from approximation are indicated as follows: ##EQU9## Said errors having an infinitely small value proportional to (ΔT 2/T₁) do not raise any practical problem. In the first stage of operation of the A-D converter of this invention, two input terminals 13a, 13b are impressed with a reference voltage V_(R) for a prescribed time period T₁. Later, both input terminals 13a, 13b are grounded to determine a time period T₂, thereby defining a required amount ΔT for automatic adjustment. A prescribed time period T₃ used in actually measuring the level of an input voltage V_(S) is determined by the equation:

    T.sub.3 = T.sub.1 - 1/2ΔT

thereafter, the first input terminal 13a is supplied with an input voltage V_(S) and the second input terminal 13b with a reference voltage V_(R) for a time equal to half the time T₃ (T₃ /2) thus determined. During the second half of the time T₃ (T₃ /2), the first input terminal 13a is conversely supplied with a reference voltage V_(R), and the second input terminal 13b with an input voltage V_(S). Thereafter, both input terminals are again supplied with a grounding voltage 0 to measure a time period T₄.

There will now be described by reference to FIGS. 3 and 5 the second stage of operation of the subject A-D converter, where both input voltage V_(S) and reference voltage V_(R) have a positive polarity. In this case, the operation of determining from T₁ and T₂ a required amount of correction for automatic adjustment of the offset of the D.C. amplifier 11 is carried out in exactly the same manner as in the first stage of operation. Both input terminals 13a, 13b are supplied with a reference voltage V_(R) and, after a time T₁, with a grounding voltage 0. Measurement is made of a time required for the level of an output voltage V_(O) from the D.C. amplifier 11 to reach that of a comparison reference voltage V_(C). This operation provides the following equation:

    T.sub.2 = T.sub.1 + ΔT

thereafter, the input terminal 13a is impressed with an input voltage V_(S) and the input terminal 13b with a grounding voltage 0 for a period from a point of time t₂ to a point of time t₃, that is, for a period equal to half the time period T₃ (assuming 0 ≦ V_(S) ≦ V_(R)). As a result, the level of an output voltage V_(O) from the D.C. amplifier 11 rises above that of the comparison reference voltage V_(C) as shown in FIG. 5. In this case, the time period T₃ is determined as follows:

    T.sub.3 = T.sub.1 + 1/2ΔT

After the first half of the time T₃, the input terminal 13a is supplied with a grounding voltage 0 and the input terminal 13b with an input voltage V_(S) for a period from a point of time t₃ to a point of time t₄, that is, for the second half of the time T₃. Later, both input terminals 13a, 13b are supplied with a reference voltage V_(R), measuring a time period T₄ required for the level of an output voltage V_(O) from the D.C. amplifier 11 to reach that of a comparison reference voltage V_(C). As a result, the following equation is obtained: ##EQU10## Since ΔT = T₂ - T₁ and T₃ = T₁ + 1/2ΔT, the ratio (V₂ /V_(R)) of the levels of the input voltage V_(S) and reference voltage V_(R) is indicated as follows: ##EQU11## Namely, the following approximation equation results: ##EQU12## In this case, a time difference is infinitely small as indicated by the following equation: ##EQU13## As apparent from the above approximation equation, the ratio (V_(S) /V_(R)) determined by the above-mentioned operation is not derived from the correction of the time period T₄, but from the correction of (T₁ - T₄).

In the second stage of operation, the two input terminals 13a, 13b are impressed with a referential voltage V_(R) for a time T₁ and later with a grounding voltage for a time T₂ to determine a required time amount of time difference ΔT for automatic adjustment of the offset of the D.C. amplifier 11. A period T₃ during which the input voltage V_(S) being measured continues to decrease is defined to be T₃ =T₁ + 1/2ΔT. The terminal 13a is supplied with an input voltage V_(S), and the terminal 13b with a grounding voltage 0 during the first half of the period T₃ thus determined. During the second half of said period T₃, both input terminals 13a, 13b are impressed with a reference voltage V_(R) to measure a period T₄.

The foregoing description refers to the case where both input terminals 13a, 13b were impressed with a reference voltage V_(R) during a period T₁ and later with a grounding voltage 0 during a period T₂ to determine a time difference ΔT. However, it also attains the object of this invention conversely to supply both input terminals 13a, 13b with a grounding voltage V_(O) during the period T₁ and with a reference voltage V_(R) during the period T₂.

The A-D converter embodying this invention is a novel form of the dual slope type A-D converter which is characterized in that it comprises two input resistors R₁, R₂ having nominally the same value of resistance. According to the subject A-D converter, the input and reference voltages V_(S), V_(R) having the same polarity are alternately appled to both input terminals 13a, 13b in the first and second stages of operation. In the first stage, both input terminals are impressed with a reference voltage V_(R) and later with a grounding voltage to determine a required amount of time difference ΔT for automatic adjustment of the offset of a D.C. amplifier included in the subject A-D converter. In the second stage, an input voltage is impressed on one of the two input terminals 13a, 13b for A-D conversion of the input voltage V_(S) with the time difference ΔT taken into account. The input voltage V_(S) is supplied to the two input terminals 13a, 13b alternately for the same period equal to half the period T₃.

Table 1 below collectively presents the manner in which the input and reference voltages V_(S), V_(R) having the positive polarity are alternately supplied in four ways to the input terminals 13a, 13b. The numerals I, II, III, IV denote the four patterns of combination in which said input and reference voltages V_(S), V_(R) are interchangeably supplied to the input terminals 13a, 13b. The character "input 1" shows a voltage impressed on the input terminal 13a, and the character "input 2" represents a voltage supplied to the input terminal 13b.

                  Table 1                                                          ______________________________________                                                    T.sub.1                                                                              T.sub.2                                                                                ##STR1##                                                                               ##STR2##                                                                             T.sub.4                                 ______________________________________                                               Input 1   V.sub.R O     V.sub.S                                                                              V.sub.R                                                                              O                                          Input 2   V.sub.R O     V.sub.R                                                                              V.sub.S                                                                              O                                          Input 1   V.sub.R O     V.sub.S                                                                              O     V.sub.R                              II                                                                                   Input 2   V.sub.R O     O     V.sub.S                                                                              V.sub.R                                    Input 1   O       V.sub.R                                                                              V.sub.S                                                                              O     V.sub.R                              III                                                                                  Input 2   O       V.sub.R                                                                              O     V.sub.S                                                                              V.sub.R                                    Input 1   O       V.sub.R                                                                              V.sub.S                                                                              V.sub.R                                                                              O                                    IV                                                                                   Input 2   O       V.sub.R                                                                              V.sub.R                                                                              V.sub.S                                                                              O                                    ______________________________________                                    

table 2 below collectively indicates the values of ΔT, T₃ and (V_(S) /V_(R) A) occuring in the above mentioned four ways in which the input and reference voltages V_(S), V_(R) are interchangeably supplied to the input terminals 13a, 13b.

                  Table 2                                                          ______________________________________                                          ΔT        T.sub.3                                                                                 ##STR3##                                             ______________________________________                                         I       T.sub.2 -T.sub.1                                                                          ##STR4##                                                                                  ##STR5##                                         II      T.sub.2 -T.sub.1                                                                          ##STR6##                                                                                  ##STR7##                                         III     T.sub.2 -T.sub.1                                                                          ##STR8##                                                                                  ##STR9##                                         IV      T.sub.2 -T.sub.1                                                                          ##STR10##                                                                                 ##STR11##                                        ______________________________________                                    

generally, a digital output from an A-D converter is so designed as to cause the specified level range of an input signal between the maximum and minimum values to correspond to a suitably determined number of digital steps. For example, a binary A-D converter is designed to produce a digital output represented by 000 . . . 00 for a maximum level of an input voltage and by 111 . . . 11 for a maximum level thereof. A number of digital steps lying between the maximum and minimum levels of an input voltage is denoted by S =(2^(m) - 1), (where m represents the bit number of a digital output from the A-D converter).

With the above-mentioned embodiment, where V_(R) represents a maximum level of an analog input voltage V_(S), and O shows a minimum level thereof, and, in the first stage of operation, a period T₁ is determined by a counted number S of clock pulses, then a clock pulse count of (T₄ - 1/2ΔT) denotes a corrected required digital output from the A-D converter. Where, in the second stage of operation, a period T₁ is determined by a counted S number of clock pulses for the same level range of an input signal, then a counted number {(T₁ - T₄) -1/2ΔT}of clock pulses represents a desired digital output from the A-D converter as seen from the equation (1).

If a maximum level of an input voltage is denoted by J_(max) V_(R) and a minimum level thereof by J_(min) V_(R) (1 > J_(max) > J_(min) > 0), a desired form of a digital output is obtained from the A-D converter by subtracting a counted S number of clock pulses multiplied by a fraction J_(min) /(J_(max) -J_(min)) from a counted number of pulses representing a digital output from the A-D converter with a period T₁ denoted by a counted S number of clock pulses multiplied by a fraction 1 /(J_(max) -J_(min)).

The point is that a suitable number of clock pulse is allotted to a period T₁ over the specified level range of an input signal, and, if necessary, a proper counted number of clock pulses is subtracted from a number of clock pulses representing a digital output from the A-D converter in order to obtain a required digital output therefrom.

Elevation of the precision with which the periods T₁, T₂, T₃, T₄ are measured is necessary to improve the operational accuracy of an A-D converter. Since the length of a period is determined by counting a number of clock pulses allotted thereto, an error as large as at least one count is unavoidable as viewed from the operational precision of the A-D converter. This difficulty can be resolved by multiplying the above-mentioned counted number of clock pulses by an integral number (a preferred multiplier being any of multiples of 2 such as 2, 4, 8, etc.) in measuring a length of time and dividing a counted number of clock pulses representing a digital output from the A-D converter which is thus multiplied by the same integral number as that used as a multiplier.

FIG. 6 illustrates a block circuit diagram of the control circuit 15 of this invention used to obtain a corrected digital output. FIG. 7 shows the operation of an updown counter 21 of FIG. 6. Referring to FIG. 6, numeral 20 denotes a switch control circuit, which controls the operation of the changeover switch 14 according to the level of an output voltage from the comparator 12, the preset of the updown counter 21 and up- and down-counting. Shift register 22 which is stored with a count made by the counter 21, applies a prescribed operation to said stored count, sends a count thus treated back to the counter 21 and produces an A-D converted value of an input signal.

There will now be described by reference to FIG. 7 the function of said switch control circuit 15 in the aforesaid first stage of operation.

When both input terminals 13a, 13b are impressed with a reference voltage V_(R), the updown counter 21 is preset at zero to count a number of clock pulses supplied to said counter 21 through an AND gate 23 (FIG. 6) up to a prescribed number N₁. This interval denotes a period T₁. When counting clock pulses up to a predetermined number, the updown counter 21 gives forth a signal to the switch control circuit 20, thereby causing the changeover switch 14 to be so operated as to impress both input terminals 13a, 13b with a grounding voltage. At this time, the updown counter 21 is changed to down counting successively to count down said prescribed number N₁ until the comparator 12 sends forth an output voltage to said updown counter 21. This interval denotes a period T₂. With a downcounted number designated as N₂, the information stored in said updown counter 21 is indicated as N₁ - N₂ = -ΔN. Said -ΔN represents a time difference ΔT. A signal showing -ΔN is transferred to the shift register 22, where the signal is shifted down by one bit to have its negative prefixed rotation to the positive to be returned to the updown counter 21, namely, to preset the updown counter 21 at ΔN/2. At this time, input and reference voltages V_(S), V_(R) are alternately supplied to the input terminals 13a, 13b, and the updown counter 21 continues counting, until the prescribed number N₁ is reached, namely, counts up to an extent of N₁ -ΔN/2 = N₃. This count denotes a period T₃. When the updown counter 21 counts up to the prescribed number N₁, the voltages supplied to the input terminals 13a, 13b are interchanged. The updown counter 21 is preset at -ΔN/2, and continues counting until the comparator 12 supplies an output voltage to said updown counter 21, that is, until a prescribed number N₄ is reached. This interval corresponds to a period T₄. The information (N₄ - ΔN/2) stored in the updown counter 21 at this time is transferred to the shift register 22, which in turn gives forth said stored number.

The output value (N₄ - ΔN/2) from the shift register 22 denotes a value of the ratio (V_(S) /V_(R) A ).

The foregoing description refers to the function of the switch control circuit 15 in the first stage of operation. All the forms of operation shown in the previous Table 2 can be carried out in the same manner.

As described above, the embodiment of this invention can attain the automatic adjustment of the offset of the D.C. amplifier 11 and admits of application of input and reference voltages having the same polarity, thus enabling ratiometric conversion to be easily effected. If the D.C. amplifier and comparator are thus operated with the same polarity, then the A-D converter as a whole can function with a single polarity, prominently simplifying the arrangement of a power source device. The A-D converter of the invention can correct errors occurring from the offset of the integration circuit I as a whole, including the offset of an input voltage appearing in D.C. amplifier, and errors resulting from any slight displacement of the level of a voltage impressed on the noninversion input terminal of the D.C. amplifier from a prescribed level of voltage (a level lying intermediate between the levels of the reference and grounding voltages).

Further, with the embodiment of this invention, a period T₃ during which the level of an input voltage is actually measured is divided into two equal parts. Namely, the voltages impressed on the two input resistors R₁, R₂ are interchanged during the first and second halves of said period T₃. Accordingly, even if the input resistors deteriorate with time or changes occur in ambient temperature, the resultant errors can be offset to zero, providing an accurate amount of A-D conversion.

The process of impressing interchangeable voltages to the input resistors during the first and second halves of the period T₃ has such advantage that even if the two input resistors do not have a fully equal value of resistance, they can realize practically the same effect. The requisite condition is that an equivalent input voltage supplied to the integration circuit I during the period T₃ be chosen to have a level equal to the mean of the levels of the input and reference voltages V_(S), V_(R) impressed on the two input terminals 13a, 13b.

The above-mentioned requisite condition is now explained in the form of a numerical equation. Where the resistance of the two input resistors are denoted by R(1+α) and R(1-α) respectively, and the first and second halves of the period T₃ are represented by T₃ (1+δ)/2 and T₃ (1-δ)/2 respectively with a time difference taken into account, then the level of an equivalent input voltage supplied to the integration circuit I may be expressed by the following equation, because the two input terminals 13a, 13b are impressed with interchangeable voltages as shown in the combination patterns I, IV: ##EQU14## In the combination patterns II, III, where the two input terminals 13a, 13b are supplied with input and grounding voltages V_(S), O, the level of an equivalent voltage on the integration circuit I is indicated as

    V.sub.S (1-αδ)/2

in a theoretically ideal case, the coefficient by which the period T₃ is divided into 2 parts is 1/2. Therefore, a time difference error can be expressed as αδ.

Conversely where various forms of voltage are not interchangeably supplied to the two input resistors during the first and second halves of the period T₃, then a difference between the values of resistance of said two input resistors appears unchanged. Said difference is expressed as α.

However, an attempt to provide such a combination of two input resistors having said resistance difference α of zero would involve high cost. Moreover, it would be extremely difficult to realize α=0 regardless of change in ambient temperature and the deterioration with time of said resistors.

On the other hand, where various forms of voltage are interchangeably supplied to the two input resistors during the first and second halves of the period T₃ as is carried out in the embodiment of this invention, the time difference is indicated by αδ. If, therefore, said period T₃ is divided into two fully equal parts, then there result δ=0 and αδ=0, easily eliminating the above-mentioned problems.

For practical purpose, it is advised to define a time difference so as to attain the required operational precision of the A-D converter. Where the same amount of time difference is utilized, this invention offers a far greater advantage in realizing said precision than the prior art A-D converter wherein input and reference voltages are not alternately supplied to the input resistors. For example, where a given A-D converter is demanded to have an error of 0.01% at most, a difference α between the values of resistance of the two input resistors should be of the order of 0.0001, if input and reference voltages are not alternately supplied to said resistors. In contrast, where the input and reference voltages are alternately supplied to the two input resistors, then αδ is only desired to have a value of, for example, 0.0001. This can be easily realized by a combination of α=0.01 and α=0.01.

As apparent from the aforesaid Table 2, all the values shown in the columns of T₃ and (V_(S) /V_(R))_(A) contain a term ΔT/2. If ΔT denotes an odd number, then there will appear a function of 0.5 in the form of ΔT/2. This fraction should be discorded or reckoned as a unit.

Where, therefore, as in the combination patterns I, IV, values given in the columns of T₃ and (V_(S) /V_(R))_(A) have the correction term ΔT/2 prefixed with the same notation, then one of the values of said two correction terms ΔT/2 should be discarded and the other should be reckoned as a unit. Then the errors of the A-D converter can be decreased. On the other hand, where, as in the combination patterns II, III, values shown in the columns of T₃ and (V_(S) /V_(R))_(A) have the correction term ΔT/2 prefixed with different notations, then the value of each correction term ΔT/2 should advisably be discarded or reckoned as a unit in order to reduce the errors of the A-D converter.

As previously mentioned, input, reference and grounding voltages are impressed on the input terminals 13a, 13b through the changeover switch assembly 14. This switch assembly 14 is generally of an electronic type. However, the response time of said switch assembly 14 is extremely short, but not zero. Moreover, a plurality of unit switches constituting said switch assembly 14 give different response times. Therefore, a time difference possibly takes place while voltages are interchangeably supplied to the input terminals 13a, 13b during the period T₃. To eliminate the occurrence of said time difference, it is advised to carry out the interchangeable supply of voltages to the input terminals 13a, 13a also during the time T₁. Normally during the period T₁, both input terminals 13a, 13b are supplied with a reference voltage V_(R) or a grounding voltage 0. If the interchangeable supply of voltages is additionally carried out during the period T₁ in the same manner as during the period T₃ purposely to introduce a time difference arising from said interchangeable supply, then a time difference caused by the interchangeable impression of voltages can be offset.

In the foregoing embodiment, the input terminals 13a, 13b were supplied with three forms of voltage, that is, input voltage, reference voltage and grounding voltage. However, the grounding voltage need not be used as such, because the grounding voltage may be deemed as a kind of reference voltage. In other words, the input terminals 13a, 13b of the A-D converter according to the embodiment of this invention may be considered to be supplied with an analog input voltage being measured and first and second reference voltages having the same polarity as the analog input voltage but different levels from each other. A voltage impressed on the noninversion input terminal of the D.C. amplifier 11 is chosen to have a level substantially intermediate between those of the first and second reference voltages, that is, a value of 1/2(VR₁ +VR₂).

The foregoing description refers to the case where the first and second reference voltages had a positive polarity (or one of said reference voltages had a zero level, but is also applicable to the case where the first and second reference voltages have a negative polarity, or one of said referential voltages had a zero level). In the latter case, the noninversion input terminal of the D.C. amplifier 11 is impressed with a negative voltage.

In the foregoing embodiment, a single reversible counter 21 was used in presetting and measuring the length of a period during which clock pulses were counted. However, a plurality of counters may be provided to measure the periods T₁, T₂, T₃ /2, T₄ separately. Or it is possible to measure the periods T₁, T₂ by one counter and the periods T₃ /2, T₄ by another counter. Thus, the number of counters may be suitably selected.

The above-mentioned process consisted in eliminating the offset voltage of the D.C. amplifier 11 in a single correction cycle on the basis of a value of an approximation equation, with the period T₁ set at a fixed value. Where, however, a corrected integrated period T₃ is used as the succeeding period T₁ being measured, then a period required for the input voltage V_(S) to be integrated in actual measurement can be determined with high accuracy. Further with the A-D converter of this invention, the period T₃ is divided into substantially equal parts, and input and reference voltages V_(S), V_(R) are alternately supplied to the two input resistors R₁, R₂ during the first and second halves of said period T₃, thereby eliminating an effect resulting from a difference between the values of resistance of said two input resistors R₁, R₂. When the above-mentioned correction operation is repeated, errors of the A-D converter caused by the offset voltage of the D.C. amplifier 11 can be gradually reduced, attaining the more accurate measurement of the level of an input voltage V_(S) and in consequence a more precise value of A-D conversion.

There will now be described the principle on which the above-mentioned correction process is based. With the periods T₁, T₂ corrected for the n-order time designated as T₁.sup.(n), T₂.sup.(n), and the periods T₃, T₄ actually measured similarly for the n-order time as T₃.sup.(n), T₄.sup.(n), there results the following equation:

    T.sub.3.sup.(n) = T.sub.1.sup.(n+1)

With the aforesaid equation (1) applied in this case, the following equation is derived:

    (V.sub.S - 2ΔV)T.sub.3.sup.(n) = (V.sub.R + 2ΔV)T .sub.4.sup.(n)

With the term 2ΔV substituted by ΔV, there is obtained the following equation: ##EQU15## Assuming the following equation: ##EQU16## is obtained. Further, as the following equation ##EQU17## can be obtained from the equation (4), ##EQU18## is established.

T_(R) in the above equation (4) denotes a length of time corresponding to the reference voltage V_(R), namely, a length of time representing the A-D converted value of said reference voltage V_(R). Counting of T₄.sup.(n) + T₃.sup.(n) - T_(R) corresponding to the input voltage V_(R) provides an A-D converted output voltage of the input voltage V_(S). If, therefore, T₁.sup.(n) is corrected to determine T₃.sup.(n) so as to establish the above equation (3), then the intended result is attained.

The equation (3) is expressed in the form of an actually measured value. If the equation (3) is applied to a correcting period by assuming V_(S) = V_(R), the following equation results: ##EQU19## Thus, ##EQU20## To establish the aforesaid equation (4), therefore, the following equation has only to be satisfied. ##EQU21## Since ΔV/V_(R) °°1 is generally accepted in the above equation (4), the primary approximation equation is expressed as follows: ##EQU22## Therefore, the following equation ##EQU23## will be a proper approximation correction equation to establish the above equation (4). As seen from the equations (5) and (6), errors caused by ΔV are reduced to zero in case of 2T_(R) = T₁.sup.(n) + T₂.sup.(n), resulting in T₃.sup.(n) = T₁.sup.(n).

There will now be described the manner in which errors of the A-D converter can be progressively absorbed, as the number n of repeated corrections increases.

Values obtainable from actual measurement are T₄.sup.(n) and T₃.sup.(n). A difference between these measured values and a truthful value of V_(S) /V_(R) is expressed as follows: ##EQU24## Now substituting the above equation (6) and the following equation: ##EQU25## then, the above equation (7) may be modified as follows: ##EQU26## Therefore, ##EQU27## Thus, the following equation results: ##EQU28## Since ##EQU29## is generally accepted, there results the following: ##EQU30## Therefore, it is seen that errors of the A-D converter linearly decrease, that is, said errors are progressively reduced and finally absorbed to a zero point as the time n of repeated corrections increases.

As apparent from the foregoing description, repeated corrections elevate the accuracy of a value of A-D conversion. The equation (6) shows that if the equation 2T_(R) = T₁.sup.(n) + T₂.sup.(n) is satisfied, it will be unnecessary to correct the period T₃. It is, therefore, advised to detect a difference between T₁ + T₂ and 2T_(R) and carry out correction so as to cause said difference to approach zero. The above-mentioned process of determining the period T₃ to be T₁ - 1/2ΔT from a time difference ΔT resulting from ΔV is generally accepted. However, T₃ may also be determined through the process of measuring (T₁ + T₂) - 2T_(R), increasing T₁ by counting up one clock pulse, in case said term (T₁ + T₂) - 2T_(R) has a negative value, and decreasing T₁ by counting down by one clock pulse in case said term has a positive value.

With an A-D converter according to a second embodiment of this invention shown in FIG. 8, reference voltages V_(R) /2 obtained through two resistors R₃, R₄ having substantially the same value of resistance are supplied to the noninversion input terminal of the D.C. amplifier 11 and the reference voltage input terminal of the analog comparator 12 respectively. Upon receipt of an output signal from the analog comparator 12, the switch control circuit 15 controls the changeover operation of the analog changeover switch assembly 14.

There will now be described by reference to FIG. 9 the arrangement and operation of a switch control circuit 15 used with the embodiment of FIG. 8. First, counters 31, 32, 33 and latch 42 are cleared by an initial clear signal. At this time, the counter 33 is brought to a state of zero, and an AND circuit 131 is opened through an OR circuit 120, causing a down clock signal to be introduced into the counter 31 for its down counting. A switch S1 is rendered conducting through an OR circuit 122 to supply a reference voltage V_(R) to the input terminals of resistors R₁, R₂. This represents the condition of the column T₁ of the combination pattern I shown in the aforesaid Table 1. The above-mentioned zero state of the counter 33 causes an AND gate 113 to be opened and in consequence the counter 32 to be supplied with an up clock signal for its up counting.

When the information stored in the counter 31 is delivered to a -T_(R) element indicating a length of time corresponding to the A-D converted value of a reference voltage V_(R), an output signal from a decoder 105 is carried through an AND circuit 114 and OR circuit 119 to the counter 33, which in turn counts up one clock pulse, and is brought to a state of 1. As the result, switches S3, S6 are rendered conducting through an OR circuit 123, and the resistors R1, R2 are impressed with zero voltage, bringing about the condition of the column T₂ of the combination pattern I shown in Table 1. When the AND gate 112 is opened through the OR gate 121 a downcounting command is applied to the updown counter 32 which in turn counts down clock pulses. When the integration circuit I produces an output whose voltage level is raised, and the analog comparator 12 generates an output having a logical value of "1", then an AND gate 115 also gives forth an output having a logical value of "1". This output is conducted through an OR circuit 119 to the updown counter 33 which in turn counts up one clock pulse. As a result, a count stored in the updown counter 33 indicates a numeral 2. An output from the AND gate 115 is delivered as a set pulse to the latch 42, which in turn is stored with the data of the updown counter 32, that is, a value of (T₁ - T₂). An output from the AND circuit 115 is delayed by a delay line 125 and the delayed output is delivered as a set pulse to the updown counter 31. A length of delay effected by the delay line 125 is chosen to be sufficient for the latch 42 to be set. An output from the latch 42 is supplied to the data input terminal of the updown counter 31 in the form shifted down by one bit, though not shown. At this time, the updown counter 31 is preset at a value of (T₁ - T₂)/2. An output from the delay line 125 is supplied as a set pulse to the updown counter 32. An output from the latch 42 is delivered to the data input terminal of the counter 32 in the form shifted down by two bits. Therefore, the updown counter 32 is preset at a value of (T₁ - T₂)/4.

An output from the decoder 108 which represents a numeral 2 actuates the switch S2 and also the switch S4 through an OR circuit 124. As a result, an input signal is successively supplied to the integration circuit I in the combined form shown in the first T₃ /2 column of the combination pattern I of Table 1. An output representing the numeral 2 from the decoder 108 also passes through an OR circuit 130 to the AND circuit 131 to supply a down clock to the updown counter 31. Further, when the 2 output from the decoder 108 is applied through OR circuit 121 to the AND gate circuit 112, the updown counter 32 is also supplied with a down clock.

When a count stored in the updown counter 32 indicates -T_(R) /2, a decoder 106 produces an output which is conducted through an AND circuit 116 and OR circuit 119 to the updown counter 33 which in turn counts up one clock pulse. Thus, a count stored in said counter 33 at this time shows a numeral 3. A length of time T which passes up to the point at which said numeral 3 is indicated after voltages are supplied to the integration circuit I in the form combined at this time is expressed as follows: ##EQU31## Therefore, the following equation results: ##EQU32## An output from the decoder 108 which shows a numeral 3 is transmitted through an OR circuit 122 to the switch S1 for its actuation, causing the resistor R1 to be impressed with a reference voltage V_(R). Said output is also delivered to the switch S5 for actuation, causing the resistor R₂ to be supplied with an input voltage V_(S). Namely, there results the condition of the second T₃ /2 term of the combination pattern I shown in Table 1. Since, under this condition, the OR circuit 130 generates an output having a logical value of "1", the updown counter 31 continues down-counting until a length of time denoted by -T_(R) is reached. A length of time T which lies between the initial point of the period T₃ and the point of time at which said T_(R) is reached is expressed as ##EQU33## Therefore, the following equation results: ##EQU34##

An output from a decoder 105 passes through an AND circuit 117 and OR circuit 119 to the updown counter 33 which in turn counts up one clock pulse to bring its stored count to a numeral 4. An output from said updown counter 33 which denotes the numeral 4 is transmitted through an OR circuit 123 to the switches 3, 6 for actuation, thereby causing the integration circuit I to be supplied with an input of zero volt, namely, bringing about the condition of the term T₄ of the combination pattern I shon in Table 1. An output from the AND circuit 117 is conducted as a set pulse to the updown counter 31 through the OR circuit 111, causing the updown counter 31 to be set at the count stored in the latch 42. An output from said updown counter 31 which represents the numeral 4 is carried through an AND circuit 120 to the AND circuit 109 to open its gate, thereby supplying an upcounting command to the updown counter 31, which in turn commences upcounting. When the analog comparator 12 produces an output having a logical value of "1", then the AND circuit 118 also generates an output having a logical value of "1", causing the updown counters 33, 32 to be reset and also the latch 41 to be set at the count stored in the updown counter 31. The count A at which the updown counter 31 is set at this time is expressed as follows: ##EQU35##

Thus, the above-mentioned operation cycle of the A-D conversion is brought to an end.

An output from the AND circuit 118 is delayed by a delay line 126. This delayed output is delivered as a set pulse to the updown counter 31, which in turn is set at a value eqaul to half a count stored in the latch 42, namely, at (T₁ - T₂)/2. At this time, as a count stored in the updown counter 33 is brought to zero, the aforesaid operation cycle may be successively commenced again. In this case, a series of operation sequence of the periods T₁, T₂, T₃, T₄ is again repeated.

However, a count stored in the latch 42 approaches, as previously described, the following value:

    T.sub.1 + T.sub.2 = 2T.sub.R,

each time the above-mentioned measurement is repeated. The process of repeating the measurement of only the periods T₁, T₂ and carrying out the A-D conversion of the periods T₃, T₄ only upon receipt of a command for said conversion from the outside can obviously be effected simply by controlling the upcounting and resetting of the updown counter 33 in a slightly modified manner.

The process of compensating for a difference between the values of resistance of the two integration resistors R₁, R₂ which was applied in the embodiment shown in FIGS. 3, 4 and 5 collectively was to divide the period T₃ in two substantially equal parts, that is, the first and second half-T₃ periods, and supply an analog input voltage V_(S) and reference voltage V_(R) interchangeably to the two resistors R₁, R₂ during said two half-T₃ periods. However, this compensation process may be effected by the following modified method, which will now be described by reference to FIGS. 3, 10, 11, 12, 13, 14 and 15.

This modified compensation method also attains ratiometric conversion even when a single input resistor is used. Namely, in FIG. 14, the two input resistors R₁, R₂ of FIG. 3 are replaced by a single resistor R. In this case, voltages are interchangeably supplied to the input terminal 13 in four combination patterns I, II, III, IV shown in Table 3 below.

                  Table 3                                                          ______________________________________                                          T.sub.1     T.sub.2                                                                                 ##STR12##                                                                               ##STR13##                                                                             T.sub.4                                  ______________________________________                                         I      V.sub.R  O        V.sub.R                                                                               V.sub.S                                                                               O                                       II     V.sub.R  O        O      V.sub. S                                                                              V.sub.R                                 III    O        V.sub.R  O      V.sub.S                                                                               V.sub.R                                 IV     O        V.sub.R  V.sub.R                                                                               V.sub.S                                                                               O                                       ______________________________________                                    

a required amount of correction for automatic adjustment of the offset voltage of the D.C. amplifier 11 is determined by supplying the input terminal 13 first with a reference voltage V_(R) and then a grounding voltage 0 for measurement of T₂.

The period T₁ is changed by said required amount of correction to define the period T₃. The input terminal 13 is impressed with a reference voltage V_(R) during the first half-T₃ period and then with an input voltage V_(S) during the second half-T₃ period. Thereafter, the input terminal 13 is supplied with a grounding voltage 0 to measure the period T₄. The switch control circuit 15 of FIG. 14 having substantially the same arrangement as in FIG. 9 can be easily operated simply by supplying different combinations of outputs from the decoder 108 to the changeover switch assembly 14. The A-D converter of FIG. 14 comprises a single input resistor R, eliminating the necessity of considering a difference between the values of resistance of the two input resistors R₁, R₂ as is the case with FIG. 3. However, it is indispensable to divide the period T₃ in two accurately equal parts.

When the period T₄ required for the analog comparator 12 of FIG. 3 to give forth an output is fully measured, the operation of the changeover switch assembly 14 is shifted to supply the input terminal 13a with a reference voltage V_(R) and the input terminal 13b with an input voltage V_(S) for a period T₃ ' shown in FIG. 10 extending from a point of time t4 to a point of time t5. The period T₃ ' is defined to be T₁ - 1/2ΔT as in the previous case.

After passage of the period T₃ ', the input terminals 13a, 13b are impressed with a grounding voltage 0 instead of an input voltage V_(S) to measure a period T₄ ' extending from a point of time t5 to a point of time t6 which is required for the level of the resultant voltage to reach the level of a comparison reference voltage V_(C).

The determined relationship existing between the periods T₃, T₄ is applicable in the same way to the periods T₃ ', T₄ '. The approximation equation denoting the ratio between the levels of the input voltage V_(S) and reference voltage V_(R) determined by the above-mentioned process of measuring the periods T₃ ', T₄ ' is expressed as ##EQU36##

When a mean is determined between a value of A-D conversion obtained by supplying, for example, an input voltage V_(S) to the input terminal 13a and a reference voltage V_(R) to the input terminal 13b and another value of A-D conversion determined by reversing the above-mentioned process, then errors of an A-D converter arising from the deterioration with time of the input resistors and variation in ambient temperature can be fully corrected.

As mentioned above, the two input terminals 13a, 13b are impressed with a reference voltage V_(R) for a prescribed period T₁ in the first operation. Thereafter, a length of a period T₂ is measured by grounding both input terminals 13a, 13b so as to define a required amount of a time difference ΔT for automatic adjustment of the offset voltage of the D.C. amplifier 11, thereby determining a prescribed period T₃ used in actual measurement of the level of an input voltage V_(S) to be T₁ - 1/2ΔT. The input terminals 13a, 13b are impressed with an input voltage V_(S) and reference voltage V_(R) for a period T₃ thus determined. Thereafter a grounding voltage 0 is supplied to the input terminals 13a, 13b to measure a period T₄. Thereafter the input voltage V_(S) and reference voltage V_(R) supplied to the input terminals 13a, 13b are exchanged for each other to measure a period T₄ '. A digital value of the input voltage V_(S) is determined from an average between the measured values of the lengths of the periods T₄, T₄ '.

There will now be described by reference to FIG. 11 the second operation, where both input voltage V_(S) and reference voltage V_(R) have a positive polarity. The same process as in the first operation is used in determining a required amount of correction for automatic adjustment of the offset voltage of the D.C. amplifier by measuring the periods T₁, T₂. Namely, the input terminals 13a, 13b are impressed with reference voltage V_(R) and, after a period T₁, with a grounding voltage 0 to measure a length of time T₂ required for the resultant voltage level to reach the level of a comparison reference voltage V_(C). Said period T₂ is determined to be T₁ + ΔT.

Thereafter, the input terminal 13a is supplied with an input voltage V_(S) and the input terminal 13b with a grounding voltage 0 for a period T₃ (assuming 0 ≦ V_(S) ≦ V_(R)). As a result, the level of an output voltage V_(O) from the D.C. amplifier 11 rises above the level of a comparison reference voltage V_(C) as illustrated in FIG. 11. At this time, a period T₃ is determined as follows:

    T.sub.3 = T.sub.1 + 1/2ΔT

after passage of the period T₃, the input terminals 13a, 13b are supplied with a reference voltage V_(R) to measure a period T₄ required for the level of an output voltage from the D.C. amplifier 11 to reach the level of a comparison reference voltage V_(C).

Accordingly, the following results: ##EQU37## Since, however, ΔT = T₂ - T₁ and T₃ = T₁ + 1/2ΔT, the ratio (V_(S) /V_(R)) of the levels of the input voltage V_(S) and reference voltage V_(R) is expressed as ##EQU38## Thus, the following approximation equation results: ##EQU39##

An error of A-D conversion occurring in this case is extremely small as expressed by the following equation: ##EQU40##

As apparent from the above approximation equation, the ratio (V_(S) /V_(R)) obtained by the above-mentioned operation does not denote the result of correcting the period T₄, but the result of correcting a value of (T₁ - T₄).

When the period T₄ is fully measured, operation of the changeover switch assembly 14 is shifted to impress a grounding voltage 0 on the input terminal 13a and an input voltage V_(S) on the input terminal 13b for a period T₃ '. In this case, the period T₃ ' is determined to be T₁ + 1/2ΔT. After passage of the period T₃ ', the input terminals 13a, 13b are supplied with a reference voltage V_(R) to measure a period T₄ ' required for the level of an output voltage V_(O) from the D.C. amplifier 11 to reach the level of a comparison reference voltage V_(C).

A digital value of the level of the input voltage V_(S) is determined from a mean between the measured values of the lengths of the periods T₄, T₄ '.

The second operation comprises the steps of impressing a reference voltage V_(R) on the two input terminals 13a, 13b during a period T₁ ; impressing a grounding voltage 0 on said input terminals 13a, 13b during a period T₂ to determine a required amount of a time difference ΔT for automatic adjustment of the offset voltage of the D.C. amplifier 11; determining a prescribed period T₃ used in actual measurement of the level of an input voltage V_(S) to be T₁ + 1/2ΔT; supplying the input terminal 13a with an input voltage V_(S) and the input terminal 13b with a grounding voltage 0 for the period T₃ thus determined; thereafter impressing a reference voltage V_(R) on both input terminals 13a, 13b to measure a period T₄ ; supplying the input terminals 13a, 13b with a grounding voltage 0 in place of an input voltage V_(S) to measure the length of the period T₄ ; and determining a digital amount of the level of an input voltage V_(S) from an average between the measured values of the lengths of the periods T₄, T₄ '.

The foregoing description refers to the case where the input terminals 13a, 13b were impressed with a reference voltage V_(R) during the period T₁ and with a grounding voltage 0 during the period T₂ to determine a time difference ΔT. However, it is considered to have the same effect, if the input terminals 13a, 13b are supplied with a grounding voltage 0 during a period T₁ and with reference voltage V_(R) during the period T₂.

An A-D converter according to the foregoing embodiment is a dual slope type comprising two input resistors R₁, R₂ having nominally the same value of resistance. With this type of A-D converter, the input terminals 13a, 13b are supplied with an input voltage V_(S) and reference voltage V_(R) interchangeably. In the first stage of operation, the input terminals 13a, 13b are impressed first with a reference voltage and then with a grounding voltage 0 to determine the offset voltage of a D.C. amplifier used with an A-D converter in the form of a time difference ΔT. In the second stage of operation, one of the input terminals is impressed with an input voltage V_(S) to carry out the A-D conversion of the level of said input voltage V_(S) with the time difference ΔT taken into account. In the third stage of operation, an input resistor corresponding to the other input terminal is supplied with an input voltage V_(S) to carry out the A-D conversion of the level of said input voltage V_(S). A final value of A-D conversion is determined from an average between A-D converted values obtained in the second and third stages of operation.

Table 4 shows all the manners or combination patterns in which various forms of voltage are interchangeably supplied to the input terminals 13a, 13b. Referring to Table 4, characters I, II, III, IV denote said combination patterns, and the character "input 1" shows a voltage impressed on the input terminal 13a and the character "input 2" represents a voltage supplied to the input terminal 13b.

                  Table 4                                                          ______________________________________                                         COMBINATION                                                                              T.sub.1                                                                               T.sub.2                                                                               T.sub.3                                                                             T.sub.4                                                                             T.sub.3 ' = T.sub.3                                                                    T.sub.4 '                            ______________________________________                                             INPUT 1   V.sub.R                                                                               O    V.sub.S                                                                             O    V.sub.R 0                                      INPUT 2   V.sub.R                                                                               O    V.sub.R                                                                             O    V.sub.S O                                      INPUT 1   V.sub.R                                                                               O    V.sub.S                                                                             V.sub.R                                                                             O       V.sub.R                            II                                                                                 INPUT 2   V.sub.R                                                                               O    O    V.sub.R                                                                             V.sub.S V.sub.R                                INPUT 1   O      V.sub.R                                                                             V.sub.S                                                                             V.sub.R                                                                             O       V.sub.R                            III                                                                                INPUT 2   O      V.sub.R                                                                             O    V.sub.R                                                                             V.sub.S V.sub.R                                INPUT 1   O      V.sub.R                                                                             V.sub.S                                                                             O    V.sub.R O                                  IV                                                                                 INPUT 2   O      V.sub.R                                                                             V.sub.R                                                                             O    V.sub.S O                                  ______________________________________                                    

Table 5 sets forth the values of ΔT, T₃, (^(V) S/V_(R))_(A), (^(V) S/V_(R))'_(A) corresponding to all the above-mentioned combination patterns:

                                      Table 2                                      __________________________________________________________________________      ΔT  T.sub.3                                                                              ##STR14##                                                                                ##STR15##                                           __________________________________________________________________________     I   T.sub.2 - T.sub.1                                                                     ##STR16##                                                                            ##STR17##                                                                                ##STR18##                                           II  T.sub.2 - T.sub.1                                                                     ##STR19##                                                                            ##STR20##                                                                                ##STR21##                                           III T.sub.2 - T.sub.1                                                                     ##STR22##                                                                            ##STR23##                                                                                ##STR24##                                           IV  T.sub.2 - T.sub.1                                                                     ##STR25##                                                                            ##STR26##                                                                                ##STR27##                                           __________________________________________________________________________

normally, an output from an A-D converter is so designed as to cause the specified level range of an input signal lying between maximum and minimum values to correspond to a suitably chosen S number of digital steps. Namely, with a binary A-D converter, for example, an output corresponding to a minimum level of an input voltage is designated as 0000 . . . 000 and an output corresponding to a maximum level thereof as 1111 . . . 111. Values intermediate between the maximum and minimum levels are indicated by a counted number of digital steps expressed as S = (2^(m) - 1) (m denoting a number of bits constituting an output from the A-D converter). The lengths of the periods T₁, T₂ are determined by counting clock pulses issued.

Where, in the foregoing embodiment, the maximum level of an input voltage V_(S) is indicated by V_(R) and the minimum level thereof by 0, (assuming 0 ≦ V_(S) ≦ V_(R)), and a period T₁ is denoted by an S counted number of clock pulses, then a counted number 1/2(T₄ + T₄ ' - ΔT) of clock pulses represents a corrected required A-D converted output. When, in the second operation, the period T₁ is denoted by an S counted number of clock pulses over the level range of an input signal, then a counted number 1/2(2T₁ - T₄ - T₄ ' - ΔT) denotes a corrected required A-D converted output.

Where the maximum level of an input voltage is expressed as J_(max) V_(R) and minimum level thereof as J_(min) V_(R) (assuming 1 > J_(max) > J_(min) > 0), then a desired A-D converted output is obtained by subtracting a counted number (J_(min) /J_(max) - J_(min))S of clock pulses from a counted number of clock pulses representing a measured output produced by an A-D converter with the length of the period T₁ indicated by a counted number (S/J_(max) -J_(min)) of clock pulses. The requisite condition for determining an accurate A-D converted output is that a properly chosen number of clock pulses be allotted to the period T₁, and, if necessary, a suitable counted number of clock pulses be subtracted from a counted number of clock pulses representing a measured output from an A-D converter.

For improvement of the operational precision of an A-D converter, it is necessary to elevate the accuracy with which the lengths of the periods T₁, T₂, T₃, T₄, T3', T₄ ' are measured. Since a length of time is measured by counting clock pulses, an error or time difference of at least one count is unavoidable. If, in such case, the above-mentioned counting number of clock pulses is multiplied by an integral number (a preferred multiplier being any of multiples of 2 such as 2, 4, 8, . . . ) and a product thus multiplied is divided by the same integral number used as a multiplier, then the above-mentioned error can be eliminated.

FIG. 12 is a block circuit diagram of a switch control circuit 15 used with an A-D converter according to another embodiment of this invention to obtain an A-D converted output corrected by the above-mentioned process. FIG. 13 illustrates the operation of said switch control circuit 15.

Referring to FIG. 12, reference numeral 20 denotes a switch control circuit, which controls the operation of the changeover switch assembly 14, the presetting of the updown counter 21 and up- and down-counting. Numeral 22 is a shift register which stores a count made by the updown counter 21 and returns the stored count to the updown counter 21 afte a prescribed operation. Numeral 23 is a mean value calculation circuit, which produces an output representing an average between the numbers of clock pulses counted during the periods T₄, T₄ '.

There will now be described by reference to FIG. 13 the operation of the switch control circuit 15 in relation to the first operation described in connection with FIG. 10.

Both input terminals 13a, 13b are impressed with a reference voltage V_(R). The updown counter 21 is preset at zero, and thereafter counts up clock pulses received through the AND gate 24 up to a prescribed number N₁. This interval denotes a period T₁. When counting up clock pulses to the prescribed number N₁, the updown counter 21 gives forth a signal to the switch control circuit 20, which in turn controls the operation of the changeover switch assembly 14 so as to cause both input terminals 13a, 13b to be impressed with a grounding voltage. At this point the updown counter 21 is shifted from up- to down-counting. As the result, the updown counter 21 continues to count down clock pulses from the prescribed number N₁ until an output from the comparator 12 is supplied to said updown counter 21. This interval represents a period T₂. When a down-counting number of clock pulses is designated as N₂, then the count stored in the updown counter 21 is indicated as N₁ -N₂₌₋ΔN. This ΔN corresponds to a time difference ΔT. Thereafter, a number of clock pulses showing -ΔN is transferred to the shift register 22, which in turn counts down the clock pulses received by one bit to change a notation prefixed before downcounting to a character denoting the previously counted clock pulses and thereafter returns a signal showing a downcounted number of clock pulses to the updown counter 21, namely, to preset it at a value of ΔN/ 2. After the input voltages are exchanged for each other, the updown counter 21 ccounts up clock pulses to the prescribed number N₁, namely, by an extent N₁ -ΔN/2=N₃. This N₃ denotes a period T₃. When the updown counter 21 counts up clock pulses to the prescribed number N₁, the input voltages are exchanged for each other. The updown counter 21 is preset at a value of -ΔN/2, and continues to count up clock pulses until said counter 21 receives an output from the comparator 12. A length of time required for the updown counter 21 to count a number N₄ corresponds to a period T₄. A count of (N₄ -ΔN/2) stored in the updown counter 21 at this time is shifted to the mean value calculation circuit 23, which is provided with a shift register for storing said count (N₄ -ΔN/2) shifted from the updown counter 21.

Upon completion of the above-mentioned operation, the voltages supplied to the input terminals 13a, 13b are exchanged for each other. The updown counter 21 is preset at ΔN/2 and counts up clock pulses to the prescribed number N₁. Thereafter the input terminals 13a, 13b are supplied with a referential voltage V_(R) in place of an input voltage V_(S). The updown counter 21 is preset at -ΔN/2 and continues to count up clock pulses until said counter 21 receives an output from the comparator 12. A length of time required for an N₄ ' number of clock pulses to be counted up represents a period T₄ '. At this time, a (N₄ ' - ΔN/2) counted number of clock pulses stored in the updown counter 21 is transmitted to the mean value calculation circuit 23.

This calculation circuit 23 determines a means value between N₄ ' - ΔN/2 now received and N₄ -ΔN/2 previously supplied thereto, and gives forth a mean value thus determined.

The foregoing description refers to the function of the switch control circuit 15 during the first operation. Said function is carried out in the same manner and with the same effect with respect to all the combination patterns of Table 5.

According to this invention, automatic adjustment of the offset voltage of a D.C. amplifier is carried out at each time of A-D conversion. Therefore, even where the offset value changes with time, an accurate value of A-D conversion is obtained. Further, the two input resistors R₁, R₂ are supplied with interchangeable voltages during the periods T₃, T₄, T₃ ', T₄ '. Therefore, an accurate value of A-D conversion can always be obtained, even where the two input resistors R₁, R₂ included in the integration circuit I deteriorate with time and ambient temperature changes.

As apparent from Table 4, the columns T₃, (V_(S) /V_(R))_(A), (V_(S) /V_(R))'_(A) of all the combination patterns I, II, III, IV include a term ΔT/2. If ΔT denotes an odd number, then ΔT/2 gives a fraction of 0.5, which should be discarded or reckoned as a unit, according as occasion demands. Namely, where the correction terms ΔT/2 of the columns T₃, (V_(S) /V_(R))_(A') (V_(S) /V_(R))'_(A) shown in the combination pattern I have the same negative prefixed notation, and similarly said correction terms ΔT/2 of the same columns indicated in the combination pattern IV have the same positive prefixed notation, then the above-mentioned fraction of 0.5 should be discarded in the former case, and reckoned as a unit in the latter case or vice versa so as to decrease errors of A-D conversion. Where the correction terms ΔT/2 of the above-mentioned columns given in the combination patterms II, III have different prefixed notations, then the fraction of 0.5 should be discarded or reckoned as a unit with respect to both combination patterns II, III.

In the foregoing embodiment, the input terminals 13a, 13b were supplied with three forms of voltage, namely, input voltage, reference voltage and grounding voltage interchangeably. However, the grounding voltage may be regarded as a kind of reference voltage and need not be used as such. With this embodiment, therefore, voltages impressed on the input terminals 13a, 13b may be considered to consist of an analog input voltage V_(S) and first and second reference voltages V_(R) having the same polarity but different levels. An input voltage supplied to the noninversion input terminal of the D.C. amplifier 11 is chosen to have a level substantially representing a midpoint between the levels of the first and second referential voltages V_(R), that is a level of 1/2(V_(R1) + V_(R2)).

The foregoing description is not only applicable to the case where the first and second reference voltages V_(R) had the same positive polarity (or one of said voltages has a zero level), but also the case where the first and second reference voltages V_(R) have the same negative polarity (or one of said voltages has a zero level). In the latter case, a voltage impressed on the noninversion input terminal of the D.C. amplifier 11 also has a negative polarity.

With the above-mentioned embodiment, a single reversible updown counter 21 was used in the presetting and measurement of time. However, it is possible to provide a plurality of counters and cause them to share in the measurement of the periods T₁, T₂, T₃, T₄. Namely, it is possible to provide counters in a suitably chosen number, for example, to cause a single counter to measure the periods T₁, T₂ and separate counters to measure the periods T₃, T₄, T₄ '. 

What we claim is:
 1. An analog-digital converter comprising a single integration resistor to which is selectively applied any one of an analog input voltage being measured, a first reference voltage having the same polarity as said analog input voltage, and a second reference voltage having the same polarity as said analog input voltage and having a value different from said first reference voltage, a D.C. amplifier having an inversion input terminal connected to said integration resistor and having a non-inversion input terminal to which is applied a specified voltage having a substantially middle value between said first reference voltage and said second reference voltage, an integration capacitor connected between an output terminal of said D.C. amplifier and said inversion input terminal, an analog comparator having one input terminal to which is connected said output terminal of said D.C. amplifier and having the other input terminal to which is applied a comparing reference voltage, a counter for counting clock pulses for a specified length of time T₁ from the point of time when said analog comparator has detected that the output voltage of said D.C. amplifier has coincided with said comparing reference voltage, a changing over means for changing over a voltage being applied to said integration resistor to said second reference voltage at the point of time when said counter has counted clock pulses for said specified length of time T₁, a first measuring means for measuring by said counter or by another counter separately provided a length of time T₂ from the point of time when said voltage being applied has been changed over to said second reference voltage by said changing-over means to the point of time when said analog comparator again produces an output signal, a first determining means for determining an error in terms of time length due to the offset voltage of an integration circuit including said D.C. amplifier from said time length T₂ measured by said first measuring means and said specified time length T₁, a second determining means for determining a specified length of time T₃ required to measure said input voltage using said time length error determined by said first determining means, a first applying means for applying said first or second reference voltage to said integration resistor for an initial half period T₃ /2 of said specified time length T₃ determined by said second determining means and thereafter applying said input voltage to said integration resistor for the remaining period T₃ /2, a second applying means for applying said second or first reference voltage to said integration resistor after said prescribed voltages have been applied to said integration resistor by said first applying means, a second measuring means for measuring by said counter or by said another counter a length of time T₄ from the point of time when said voltage being applied to said integration resistor by said second applying means has been changed over to the point of time when said analog comparator again produces an output signal, and a means for obtaining a digital amount of said input voltage from said time length T₄ measured by said second measuring means and said specified time length T₁.
 2. An analog-digital converter comprising first and second signal input terminals to which is selectively applied through an analog switch means any one of an input analog voltage, a first reference voltage and a second reference voltage; an integration circuit having first and second integration resistors selectively connected to said first and second signal input terminals, a D.C. amplifier having an inversion input terminal to which said first and second integration resistors are connected and a non-inversion input terminal to which is applied a specified voltage having an intermediate value between said first and second reference voltages, and an integration capacitor connected between an output terminal of said D.C. amplifier and said inverstion input terminal; an analog comparator having a first input terminal connected to said output terminal of said D.C. amplifier and a second input terminal to which is applied a comparing reference voltage; and a control circuit for selectively applying through said analog switch means any one of said analog voltage, said first reference voltage and said second reference voltage to said first and second signal input terminals upon receipt of an output signal of said analog comparator, characterized in that said control circuit comprises a counter for counting clock pulses for a specified length of time T₁ from the point of time when said analog comparator has detected that the output voltage of said D.C. amplifier has coincided with said comparing reference voltage, to produce an output signal while said first reference voltage is applied to said first and second signal input terminals, a changing-over means for changing over a voltage being applied to said first and second signal input terminals to said second reference voltage at the point of time when said counter has counted clock pulses for said specified length of time T₁, a first measuring means for measuring a length of time T₂ from the point of time when said voltage being applied has been changed over to said second reference voltage by said changing-over means to the point of time when said analog comparator again produces an output signal, a first determining means for determining from said time length T₂ measured by said first measuring means and said specified time length T₁ an error in terms of time length due to the offset voltage of said integtation circuit, a second determining means for determining a specified length of Time T₃ necessary to measure said input voltage using said time length errors determined by said first determining means, a first applying means for applying said input voltage to said first signal output terminal for an initial substantial half period T₃ /2 of said specified time length T₃ determined by said second determining means and simultaneously applying said first or second reference voltage to said second signal input terminal and thereafter applying said reference voltages applied during said initial substantial half period T₃ /2 to said first signal input terminal for the remaining substantial half period T₃ /2 and simultaneously applying said input voltage to said second signal input terminal, a second applying means for applying, after said prescribed voltages have been applied by said first applying means to said first and second signal input terminals, said first or second reference voltage to said first and second signal input terminals, a second measuring means for measuring a length of time T₄ from the point of time when a voltage being applied by said second applying means has been changed over to the point of time when said analog comparator again produces an output signal, and a second determining means for determining a digital amount of said input voltage from said time length T₄ measured by said second measuring means and said specified time length T₁.
 3. An analog-digital converter according to claim 2, characterized in that said control circuit comprises a counter for counting clock pulses for a specified length of time T₁ from the point of time when said analog comparator has detected that the output voltage of said D.C. amplifier has coincided with said comparing reference voltage, to produce an output signal while said first reference voltage is applied to said first and second signal input terminals, a changing-over means for changing over a voltage being applied to said first and second signal input terminals to said second reference voltage at the point of time when said counter has counted clock pulses for said specified length of time, a first measuring means for measuring by said counter separately provided a length of time T₂ from the point of time when said voltage being applied has been changed over to said second reference voltage to the point of time when said analog comparator again produces an output signal, a first determining means for determining an error in terms of time length due to the offset voltage of an integration circuit including said D.C. amplifier from said time length T₂ measured by said first measuring means and said specified time length T₁, a second determining means for determining a specified length of time T₃ required to measure said input voltage using said time length error determined by said first determining means, a first applying means for applying said input voltage to said first signal input terminal and simultaneously applying said first or second reference voltage to said second signal input terminal for said specified time length determined by said second determining means and thereafter applying said second or first reference voltage to said first and second signal input terminals, a second measuring means for measuring by said counter or by said another counter separately provided a length of time T₄ from the point of time when said voltage being applied by said first applying means has been changed over to the point of time when said analog comparator again produces an output signal, a second applying means for applying said first or second reference voltage to said first signal input terminal and simultaneously applying said input voltage to said second signal input terminal for said specified length of time T₃ after said time length T₄ has been measured by said second measuring means and thereafter applying said first or second reference voltage to said first and second signal input terminals, a third measuring means for measuring by said counter or by said another counter separately provided a time length T₄ ' from the point of time when said voltage being applied to said signal input terminal by said second applying means has been changed over to the point of time when said analog comparator again produces an output signal, and a means for obtaining a digital amount of said input voltage using said time length T₄ ' measured by said third measuring means and said time length T₄.
 4. An analog-digital converter according to claim 2 wherein one of said first and second reference voltages is a ground level and the other is the same polarity as that of the input analog voltage.
 5. An analog-digital converter comprising first and second signal input terminals to which is selectively applied through an analog switch means any one of an input analog voltage, a first reference voltage and a second reference voltage; an integration circuit having first and second integration resistors selectively connected to said first and second signal input terminals, a D.C. amplifier having an inversion input terminal to which said first and second integration resistors are connected and a non-inversion input terminal to which is applied a specified voltage having an intermediate value between said first and second reference voltages, and an integration capacitor connected between an output terminal of said D.C. amplifier and said inversion input terminal; an analog comparator having a first input terminal connected to said output terminal of said D.C. amplifier and a second input terminal to which is applied a comparing reference voltage; and a control circuit for selectively applying through said analog switch means any one of said analog voltage, said first reference voltage and said second reference voltage to said first and second signal input terminals, characterized in that said control circuit comprises a first changing-over means for changing over said analog switch means so as to apply said input voltage and either one of said first and second reference voltages to said first and second integration resistors, a second changing-over means for changing over said analog switch means so as to apply one of said first and second reference voltages to said first and second integration resistors commonly, a third changing-over means for changing over said analog switch means so as to apply said input voltage and either one of said first and second reference voltages which is same as said first changing-over means to said first and second integration resistors respectively in a manner combined differently from said first changing-over means, and means for obtaining a digital value corresponding to a sum of output voltages of said integrator obtained by said first, second and third changing-over means, whereby an A-D converted amount of said input voltage is obtained using said digital value obtained by said last means.
 6. An analog-digital converter according to claim 5, characterized in that said control circuit comprises first and second counters for counting the clock pulses suppled at prescribed intervals, a first means for selecting said first reference voltage by said analog switch means and setting said first counter to a count-up condition, a second means for, when a count of said first counter has been arrived at a count T_(R), selecting said second reference voltage by said analog switch means to apply the second reference voltage to said D.C. amplifier and setting said second counter to a count-down condition, a first memory circuit for storing therein the count of said second counter upon receipt of an output signal of said analog comparator produced by said second means when the output voltage of said D.C. amplifier has reached said comparing reference voltage, a third means for setting a value of one-half at first memory circuit to said second counter and setting a value of one-fourth at first memory circuit to said first counter after said analog comparator produces an output signal and selecting said analog input voltage by said analog switch means and setting said first and second counters to a count-down condition, and activating said first changing-over means, a first detecting means for detecting the coincidence between a count of said first counter and a value -T_(R) /2, a fourth means for, when said detecting means has detected said coincidence, activating said third changing-over means, a second detecting means for detecting the coincidence between a count of said second counter and a value - T_(R), a fifth means for, when said second detecting means has detected said coincidence, activating said second changing-over means, and setting to the second counter (T₁ -T₂)/2 from which the second counter commences its counting operation, and a second memory circuit for storing therein the count of said second counter upon receipt of an output signal of said analog comparator produced by said fifth means when the output voltage of said D.C. amplifier has reached said comparing reference voltage.
 7. An analog-digital converter according to claim 5, wherein one of said first and second reference voltages is a ground level and the other in the same polarity as that of the input analog voltage. 